Si5351 Spurius preformance

As some of you know, I have done a lot of work with the Si5351 series of synthesizers. In a couple of blog post, I will try to document some of the more subtile details of operation of this chip. Since I don’t have access to the actual mask sets for the chips some of these statements are qualified guessing, based on observations by NT7S and myself.

I believe the routing in the chip to be more complicated than outlined in the datasheet. Trying to determine where the spurious responses come from, and why they have their amplitudes have shown some of the internals that I will try to outline. Lets start with the block diagram, shamelessly stolen from SiLabs:


The Synthesizer consists of a crystal oscillator (or TCXO/OCXO) with drivers. The performance of this is depending on the signal quality. A good designed crystal oscillator with a limiter will outperform the internal oscillator on phase noise.  Notice that the C version has a switching matrix after the oscillator and the option to feed in an external clock. This is a nice option for those cheap OCXO’s that are on non-integer frequencies.

A bit interesting is it that the datasheet mentions 25MHz and 27MHz as the alternative frequencies, but the chip works on a broad range. That 26MHz crystal will work just fine. I do believe the input frequency are divided down to  5MHz, before being distributed internally. This would then be routed out to PLL A and B, microcontroller (for the I2C) and probably to the multisynth stages as a clock.

There are both internal and external capacitors to the device. A interesting point is that when using regular crystals the spurious products seems to be reduced when selecting the internal capacitors, unlike loading with external capacitors.


The above picture is taken with PLL A set to 870MHz and the multisynth set to 6. There is up to 10dB difference between the 0pF (blue plot) and 10pF (red plot), using the internal capacitors. Selecting the 0pF internal capacitor, and using external 18pF, lead to a 10dB increase in spurs above what can be seen above. I should point out that while there are some spurs, they are not a deal breaker in this case, the above spurs can easily be removed by bandpass filtering if necessary.

The PLL’s seems to be a fairly common design, with a PLL bandwidth of around 200KHz (there are some subtile spurs). The PLL operates over the range 600MHz-900MHz. This part is the well-behaved part of the chip.

The “Multisynth” is the unknown part of the chip. I believe this is some kind of fractional divider,  clocked by the PLL signal and the 5MHz internal clock. The output spurs are reduced when the divider is operated at integer divisions instead of fractional divisions. Some experiments suggest that the multisynth is followed by a divide-by-2, as the output always have a 50% duty cycle square wave.

The way to get the best performance is to lock the Multisynth at a suitable integer level, and move the PLL to do the frequency change.  The output should be used with a switching type mixer (DBM with diodes in saturation or switches) in order to get the best preformance. A good limiter could reduce the spurious responses, perhaps reducing the voltage to the output buffer would help in driving them deeper into saturation, and giving better limiting action?

ADDITION 31. dec 16: The above plot is the worst case I have been able to make by abusing the Si5351. This is not at all typical performance. The 200KHz spurs is usually found at an amplitude less than -110dBc, and other spurious products should be below -70dBc. In my opinion, the chip is well suited as local oscillator in a receiver. 

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Mitsubishi MOSFET VHF hybrids

The last 15 years there have been a large development in MOS hybrid preformance, combined with a reduction in price, making these hybrid amplifiers quite a reasonable choice for a power amplifier in a VHF or UHF transceiver.

This hybrid is the Mitsubishi RA07H0608M made for the 60-88MHz range. I have been using these for experiments in the 70MHz band with both linear modes and FM. This hybrid should work on 50MHz, but determining the optimal bias point for linear would require the ability to do 2-tone testing.

I managed to burn out one of the amplifier modules due to self oscilations, and wanted to do some reverse engineering of what’s in the hybrid.

This hybrid is  a thick film hybrid with 2 MOSFET dies, one for the PA and one for the driver in addition to biasing and impedance maching components. The white goop is probably non-acidic sillicone used to attach the plastic casing to the substrate and cooling tab.



The driver amplifier is a vertical MOS die, approximately 1mm x 2mm in size and with 2 bond wires to the base, and 3 to the drain.


The PA transistor is a fairly large vertical MOS device, with 2 clearly visible trenches and several bonding wires on the drain. This is to reduce the inductance in the bonding wire and carry enough current. The die is quite large, approx 3mm x 3mm in size. There are some interconnections on the top of the die, but due to the passivation and sillicone around the die, its difficult to see the connections clearly.


A interesting thing is how one pass wires over antother. The hybrid consists of  a ceramic base (called substrate), with a groundplane on the backside that are bonded to the cooling tab. Traces is then put on the top of the ceramic substrate and fused together by firing. In order to make a wire pass over another, the  bottom wire is laid down and fired (heated in a furnace to a given temperature), then a isolating layer is laid down and fired before the other trace is laid down and fired. This is done because there is only one layer avaible to put traces on, and having extra wire connections to the hybrid is expensive. The opague isolator as shown are probably BeO, although the datasheet don’t mention that there is BeO in the device. BeO dust is toxic.

The traces shown here is  the bias line to the PA FET passing over the drain supply to the driver FET.


Another interesting thing about this hybrids are the extensive use of 0402 and 0603 resistors and capacitors. With thick film hybrids, its quite possible to put the resistors directly on the substrate. A reason to not do that in a amplifier like this may be that the resistors will have a termal gradient and that the resistors would require expensive laser trimming.  High value capacitors like those used for decoupling are hard to make on a hybrid like this, so soldering in regular SMD components, and even electrolytics some times.

The PA FET has negative feedback to reduce gain and improve stability, while I could not see any for the driver. There seems to be some damage to my module there, could I have blown that off the hybrid? The increase in drive level by adding some light feedback to the driver may be worth a experiment.

The output and input matching looks to be of the lowpass kind, and on the output there are some harmonic supression. The RF design here clearly outperforms the mechanical and cooling. Interfacing these modules into circuits that once held older bipolar hybrids may not be straigth forward. There is a lot of gain to several GHz avaible in the FET’s and the grounding needs to be good to avoid oscillations.

Overall, the reverse engineering of these modules were quite interesting.  A interesting thing to do may be to trace out the shcematic, although it should look like most any of the other modules available. Curve tracing the FET could be interesting to determine their parameters.

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A notch filter for phase noise measurment

Measuring phase noise is difficult, due to the large difference between the signal and the noise.  Here I will outline the method I use to determine the noise of a oscillator and show the basic bandpass – notch filter used to reduce the carrier level to a level that the common spectrum analyzer can handle.   The filter shown here will be made for 9MHz, but other frequencies can be realized as long as high Q matched crystals can be found.

When doing these measurements, reducing the noise figure of the spectrum analyzer, and knowing the inserted gain is important. I use a module with a ERA-2 MMIC mounted in a die cast box with extended filtering on the DC input.

The filter module start with a QTC (Quad Tuned Circuit) mixed form bandpass filter.  This is built and tuned for a flat bandpass before the notch


After the filter is built and tuned the crystals are connected over the 2 resonators in center and the filter is adjusted to have a as flat as possible passband. This way, with crystals matched as close as possible (2Hz) the notch depth should be better than 80dB. If the crystals can’t be matched, then a trim capacitor can be placed in series with the crystal, but this makes the tuning of the notch depth much more difficult.


The obtained filter does not need to have the notch in the center of the passband. the 3dB points of the filter will be what limits the bandwith of your measurement. If the crystals have high Q and no spurious responces (mine had some) then the passband should be flat. If there is some spurious responces, you can average it out on most spectrum analyzers. Knowing the width of the notch at the 3dB point determines how close to the carrier you can measure the phase noise.


To use the filter with a spectrum analyzer, you add a low noise amplifier with known gain at the frequency you operate on between the filter and the spectrum analyzer. Add a variable attenuator in front of the filter and set this to max attenuation before connecting it to the signal source.

Tune the signal source to the frequency where it is attenuated the most by the filter and reduce the attenuation to 0. If The noise level around the notch should be somewhat higher than the attenuated carrier.

If the spectrum analyzer have a marker that can show the amplitude level in dBm/Hz then the level of the phase noise in dBc is: Source output power(dBm) + noise amplitude (dBm) + (loss through filter in dB) – (amplifier gain in dB). For example, lets assume my source is at 10dBm, the measured noise level at -115dBm,  2.4dB filter loss and 20dB gain:  10dBm + (-115dBm/hz) + (-2.4dB) –  (20dB) = -127dBc/Hz phase noise.

If the analyzer does not have a marker function then you need to know the bandwith of the IF filter in the analyzer in addition to the parameters above.  The total equation would then be: Source output power(dBm) + noise amplitude (dBm) + (loss through filter) – (amplifier gain) – 20*log(analyzer bandwith in Hz ).   For example, source at 10dBm, measured noise level at -105dBbm in 100Hz bandwith, 2.4dB filter loss and 20dB gain: 10dBm + (-95dBm) +(-2.4dB) – (20dB) -(20*log(100)) = -147dB/Hz phase noise.


Accurate noise measurements are not easy to do. Careful evaluation of all used components and careful measurements with averaging of the traces helps to obtain accurate measurements. Alternative methods use phasing or PLL methods, and have better accuracy over a larger bandwidth, at the expence of a more advanced measurement setup.

Update February 2015:

Did a measurement of the HP8656B signal generator using the notch filter and a ERA-2 amplifier with 15.7dB gain:



The input signal into the notch filter were 0dBm and the notch filter loss 2.4dB. The total equation will then be: 0 +(-106.1dBm/Hz) + (-2.4dB) -15.7dB = -124.2dBc/Hz at the point 10KHz offset from the carrier.  This value corresponds well with other methods used to measure the phase noise on this generator. The value is 10dB better than the than what the datasheet states as worst case phase noise, not uncommon for HP equipment from the 1980s era.

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SMD prototyping

I was asked about the method I use for making small PCB’s with SMD components.

Here is a video showing the process:

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Any benefit to grounding crystal cases?

An while ago, I was asked about if there was any benefit to ground the crystal case when using them in ladder filters. I provided an quite simplified analysis and a VNA picture. After some more thinking about it I decided to extend the analysis, as the simplified version does not cover it complete.

The crystal model we use is an simplification into known components that makes the analysis of the crystal possible with easy means:



An extension of this model is to extend the capacitor C0 into 3 capacitors.



The series resonance consisting of Lm, Cm and ESR can for frequencies outside the resonance range, be assumed to be high impedance and can be somewhat simplified to an voltage divider.


By grounding the case of the crystal, the capacitor C1 and C2 gets added to the shunt capacitors for the filter, while when the case is ungrounded the series connection of the capacitors add to the capacitor C0, leading to more of the signal leaking through at the stop-band.

A sweep from an VNA of a filter ungrounded (blue) and grounded (red) show how the stop-band attenuation changes


By taking a couple of measurements off several common HC49 528MHz crystals, I obtained the following results: C0=3.4pF, C1 = 2pF, C2=2.1pF.

This data correspond quite well to the rule used by several experimenter of C0=220Cm+1pF. The 220Cm part is due to the physics of the AT cut crystal. An different crystal will have different constants due to the physics of the crystal. The 1pF will be the result of the series connected capacitors C1 and C2.

As this simple analysis show, there is a benefit to ground the crystals. Most modern crystals are welded, and you will need quite a lot of heat to do damage to the crystal, while older crystals may be soldered. The stability of the crystal will be depending on the atmosphere inside the crystal. Some crystals change their parameters quite a lot when opened, while others don’t change at all, so avoid soldering directly to the old style crystals.

Posted in Crystal, Filter, VNA | Leave a comment

IMD measurment generator

IMD or Intermodulation distortion testing is in RF systems usually done with 2 signal sources, quite close in frequency, and one determines the level of the unwanted responses. The actual measurement procedure is shown quite well other places in the literature [1].

Here I will show my design for an high performance crystal controlled RF source delivering 100mW or so into 50 ohm at HF. The obtained phase noise from this generator are better than the resolving bandwidth of my phase noise measurement -140dBc so there should not be any problems from the phase noise of the signals.


The oscillator circuit used is an common base Butler circuit, as described in Matthys [2]. There are a total of 5 frequency dependent components, the crystal, the inductor, and 3 capacitors. The oscillator have limiting to reduce the oscillation amplitude and to improve the frequency drift.


C5+C8 is selected such that the middle value falls in the center of the trimmer C5 range. The chosen crystal should be an HC49 size, not one of the smaller models, as those tend to drift more than their larger counterparts. Measured drift for this oscillator on 3.7MHz is less than 10Hz from start (red trace). Crystals can be ordered from [3] or [4]. Crystal ovens are not recommended, if temperature drift is a problem, fit the crystal with an Styrofoam bead to insulate.


The oscillator is followed by an 3. order low-pass filter to remove harmonic products from the limiting of the oscillator. There exists several types of filter one can use if one wants, I have calculated the values for an half wave filter. This have the simplicity of calculation that the reactances of the components are equal to the system impedance. In this case, for an given frequency :

where f is the crystal operating frequency in Hz. Different filter topologies like Chebychew or Butterworth can be used to improve the harmonic attenuation of the filters. Information on the calculations of such filters can be found in [1]

Following the filter is an attenuator that can be inserted if the max output level is higher than the desired operating amplitude. Suitable attenuator values can be found several places on the internet. If not used, insert an 0 ohm resistor into R8.

The attenuator is followed by an variable gain hybrid cascade amplifier. This consists of an cascade of an J-fet (MMBT310) and an bipolar transistor (BC847). The J-fet is impedance matched to the 50 ohm system with an balun made by winding 4 turns bifilar on an BN-43-2402 ferrite binocular core. The output is in an similar way matched to the power amplifier with an transformer wound on an BN-43-2402 core. The primary side against the hybrid cascade consists of 12 turns, the side against the power amplifier consists of 2 turns. Wind these such that the leads protrude on each side of the core. The amplifier gain can be adjusted with the trimmer R11 such that the output amplitude is at an fixed level, or this can be taken to an potentiometer mounted in the box such that the output power can be varied if needed.

The power amplifier consists of an NE46134 medium power RF transistor, operating in class AB and delivering a nominal 100mW output power. The inductor is wound on an FT37-43 ferrite core, and 10 turns should suffice for all HF frequencies. Following this is an order low-pass filter. This filter uses the same capacitor and inductor values as calculated for the 3. order filter before. Observe that C23 is double the value of the other capacitors. The inductors should be wound on iron core toroids. T37 size is recommended. -2, -7 and -10 material should fit the frequency range from 2MHz to 50MHz.



The PCB for this design is available from OSHpark:  3 boards for $36 with delivery worldwide.

The PCB have 2 small isolated holes on each side of the crystal and transformer to secure those to the PCB. The PCB is made to fit inside an Hammond 1590B die cast enclosure. All the used components are 0805 size. 1206 should fit, although a bit large.

In order to combine the generators, some kind of combiner is needed. There exists several kinds of couplers that are common to combine generators. 6dB hybrids are easy to construct and work over an large frequency range. For an small bandwidth range, like these crystal controlled oscilators, an Wilkinson divider gives 3dB split, and are easy to construct.

The PCB for the Wilkinson splitter can be ordered from OSHpark: 3 boards for $9.90 with delivery worldwide.


A limited amount of kits may be available from me. Documentation and PCB files available on request.

[1] Hayward et. all, Experimental methods in RF design (EMRFD).
[2] Matthys, Crystal oscillator circuits.
[3] Expanded spectrum systems
[4] ICM

Posted in IMD, Instruments, OSH, Uncategorized | 2 Comments

open T-check

Ok, since this blog seems to be about the software I write, and not about RF engineering, altough this may be related.

T-check is an routine by R&S to verify the validity of network analyzer SOLT calibration.  This is explained in the R&S application note 1EZ43_0E, covering the math behind the routine as well as the T-checker, an coaxial adapter with an integrated 50 ohm resistor. An simplified method to realize this may be an T adapter with an 50 ohm termination on the 3. port.


The VNA is calibrated and this device is inserted instead of the DUT. The S-parameters are then saved and run through the T-checker program.


The program, as supplied from R&S does only work on 32bit computers.  I made an implementation that run on both 64bit and 32bit windows as well as linux, BSD, UNIX, OSX and even Playstation 3 with MONO.

My implementation, named “open T-check” are avaible here

Posted in Instruments, Network Analyzer, T-check, Uncategorized, VNA | Leave a comment